Qualcomm DFT Engineer - Sr Engineer / Staff level in San Diego, California
Company:Qualcomm Technologies, Inc.
Job Area:Engineering Group, Engineering Group > ASICS Engineering
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.
The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
4+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is required
Understanding of core-based test methodology and scan isolation.
Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
Experience with industry EDA ATPG and insertion tools.
Familiarity with System Verilog, UVM, and use of assertions during verification, is preferred.
Detail oriented with strong organizational, problem solving, and communication skills
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