Microchip Technology Intern - Engineering in Roseville, California
The Architecture Co-Verification team is an exciting, fast paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SOC) devices using industry leading HW emulators (such as Cadence Palladium) and FPGA based prototyping platforms (such as Cadence Protium). The team is deployed in all aspects of SoC development phases including architectural exploration, HW/FW co-development, pre-silicon functional co-verification, pre/post silicon performance testing, power analysis, and critical post-silicon investigations. As a Verification Engineering Intern, you will be working closely with hardware designers, firmware engineers, and verification teams throughout the SoC development process. This is a role for a versatile Intern that enjoys the challenges of HW/FW co-development and system level co-verification using leading edge HW emulators and FPGA platforms. It’s a high visibility role that will develop a wide range of skills and exceptional problem solving ability. Responsibilities could include, but are not limited to, the following:
Porting SoC RTL to industry leading HW emulators and FPGA platforms.
Developing emulation specific HW for pre-silicon subsystem/system level co-verification.
Developing common test ecosystem across pre/post silicon.
Developing FW/tests for pre-silicon subsystem/system level co-verification.
Troubleshoot and resolve complex problems in embedded real-time systems executing co-verification test plans.
Effectively present technical information to small teams of engineers.
Enrolled in current EE/CE BS or Masters degree.
Excellent analytical, communication and documentation skills.
Excellent debug and problem solving skills.
Willing to learn in a fast paced environment, being a self-starter, and organized.
LINUX experience and good programming / scripting skills with languages such as Python, Tcl, C and Perl.
Familiarity in C/C++ FW development.
Familiarity in system level co-verification techniques.
Familiarity with hardware design and implementation.
RTL experience with VHDL, Verilog, and System Verilog.
Knowledge of protocols such as SAS/SATA and PCIE /NVME.
Knowledge of MIPS and/or ARM CPU architecture and firmware programming.
Knowledge of source control systems such as subversion or perforce.
Equal Opportunity Employer
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Applicants with Disabilities
If you need accommodation for any part of the employment process because of a medical condition or disability, please send us an email here with "Applicant Accommodation Request" in the subject line of the email. Alternatively, you may call us at 480-730-7330 to let us know the nature of your request.