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Randstad Hardware Design Engineer, FPGA in Raleigh, North Carolina

Hardware Design Engineer, FPGA

job details:

  • location:Raleigh, NC

  • salary:$95,000 - $130,000 per year

  • date posted:Thursday, February 25, 2021

  • job type:Permanent

  • industry:Professional, Scientific, and Technical Services

  • reference:823950

job description

Hardware Design Engineer, FPGA

job summary:

We have a direct FTE role for a Hardware Design Engineer FPGA in Raleigh, NC. Responsibilities include FPGA design knowledge. Must be capable of RTL design, simulation, physical implementation and verification of complex FPGA modules comprising a mix of custom RTL with hard and soft vendor IP cores within a larger architecture. Must be able to validate compliance to performance constraints, perform static timing analysis and develop functional simulations to ensure proper implementation.

Qualified Candidates will have:

  • BSEE, BSCE or equivalent degree (transcripts required)

  • Minimum 3+ years experience in digital design development, implementation & debug.

  • Experience with RTL coding using SystemVerilog, Verilog or VHDL, all are desirable.

  • Ability to develop automated self-checking test benches and verify HDL code.

  • Hands on experience using Xilinx Vivado design suite.

  • Experience with static timing analysis and optimizing logic design for timing closure.

  • Experience designing signal processing functions for video and image processing is desirable.

  • Excellent communication skills (written and verbal)

  • attention to detail, highly organized, computer literate

  • Ability to work well in a fast-paced professional office environment

location: Raleigh, North Carolina

job type: Permanent

salary: $95,000 - 130,000 per year

work hours: 9am to 6pm

education: Bachelors

responsibilities:

Responsibilities include strong FPGA design knowledge. Must be capable of RTL design, simulation, physical implementation and verification of complex FPGA modules comprising a mix of custom RTL with hard and soft vendor IP cores within a larger architecture. Must be able to validate compliance to performance constraints, perform static timing analysis and develop functional simulations to ensure proper implementation.

Qualified Candidates will have:

  • BSEE, BSCE or equivalent degree (transcripts required)

  • Minimum 3+ years experience in digital design development, implementation & debug.

  • Experience with RTL coding using SystemVerilog, Verilog or VHDL, all are desirable.

  • Ability to develop automated self-checking test benches and verify HDL code.

  • Hands on experience using Xilinx Vivado design suite.

  • Experience with static timing analysis and optimizing logic design for timing closure.

  • Experience designing signal processing functions for video and image processing is desirable.

  • Excellent communication skills (written and verbal)

  • strong attention to detail, highly organized, computer literate

  • Ability to work well in a fast-paced professional office environment

qualifications:

  • Experience level: Experienced

  • Minimum 5 years of experience

  • Education: Bachelors (required)

skills:

  • Electronics (3 years of experience is required)

  • Xilinx

  • digital design development (3 years of experience is required)

  • RTL Coding

  • SystemVerilog, Verilog or VHDL

  • static timing analysis

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

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