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Tarana Wireless Senior ASIC Engineer in Milpitas, California

This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products

  • Architecture and micro-architecture of digital subsystems

  • RTL design of digital circuits using Verilog

  • Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs

  • Chip level integration and verification

  • RTL design and integration of large functional blocks in the modem - Development, assessment and refinement of RTL design to target power, performance, area and timing goals

  • Write design documents including detailed interface descriptions and design descriptions

  • Work with Verification Engineers to develop specifications and test plans. Ensure robust design and complete coverage

  • Work with Emulation teams to test the design on various emulation platforms

  • Work with Software and Systems teams on system verification and system integration

  • Writing test cases and test benches to verify functionality of designs


  • Knowledge of C and Verilog

  • Working knowledge of scripting languages such as Python

  • Excellent communication skills


  • BSEE required / MSEE preferred

  • A minimum 3 years of experience in SoC design

  • Experience with Synthesis, Lint, CDC and other standard ASIC development tools


  • Design or integration of ARM, MIPS, Risc-V, ARC or other processors

  • Design or integration of DDR controllers

  • Knowledge or experience with Digital Signal Processing, or Channel Coding.

  • Knowledge of wireless protocols such as 802.11a/b/g/n/ac or hands-on experience with LTE/4G/5G

  • Knowledge or experience with Ethernet packet processing

  • Experience with embedded software development

  • Experience with emulation platforms

  • Experience with post silicon bringup.