Apple Senior Standard Cell APR - QA Engineer in Cupertino, California
Senior Standard Cell APR - QA Engineer
Santa Clara Valley (Cupertino),California,United States
Hands on experience in library development, understanding of EDA views and their interaction with physical design flows.
Familiar with development of testchip block for silicon validation of stdcells and megacells.
Familiarity of ASIC integration flows including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies.
Proficiency in: static timing analysis, Verilog/VHDL, formal verification, lint checks, multi-clock and power domain designs.
Strong written/verbal communication skills.
Experience with ECO implementation, both functional and timing closure.
Familiarity with DFT insertion, and multi-mode timing constraints.
Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. In this role, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure and signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose block consisting of library cells for complete Silicon Validation.
Education & Experience
BSEE / MSEE is required.
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